Datarol-II: A Fine-Grain Massively Parallel Architecture
نویسندگان
چکیده
In this paper, we introduce the Datarol-II processor, that can e ciently execute a ne-grain multi-thread program, called Datarol. In order to achieve the e cient multi-thread execution by reducing context switching overhead, we introduce an implicit register load/store mechanism in the execution pipeline. A two-level hierarchical memory system is also introduced in order to reduce memory access latency. The simulation results show that the Datarol-II processor can tolerate remote memory access latencies and execute a ne-grain multi-thread program e ciently.
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